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*.erc
*.log
**/libraries
**/research_log
\ No newline at end of file
%% Cell type:code id: tags:
``` python
ses=open('paperbot_ee.ses','r').read().splitlines()
```
%% Cell type:code id: tags:
``` python
pathsec_list=[]
for i in range(len(ses)):
if 'path' in ses[i]:
for j in range(i,len(ses)):
if ')' in ses[j]:
pathsec=[i,j]
break
```
%% Output
25
31
36
43
%% Cell type:code id: tags:
``` python
```
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(session paperbot_ee.ses
(base_design paperbot_ee.dsn)
(placement
(resolution um 10)
(component J1
(place J1 1150000 910000 front 270)
)
(component U1
(place U1 1040000 461000 front 90)
)
(component T1
(place T1 870000 900000 front 0)
)
(component L1
(place L1 670000 410000 front 90)
)
(component R1
(place R1 720000 410000 front 270)
)
)
(was_is
)
(routes
(resolution um 10)
(parser
(host_cad "KiCad's Pcbnew")
(host_version "5.1.3-ffb9f22~84~ubuntu18.04.1")
)
(library_out
)
(network_out
(net 3v3
(wire
(path F.Cu 20000
1208927 769036
1208927 581620
)
)
(wire
(path F.Cu 20000
1251600 929529
1208927 886856
1208927 769036
)
)
(wire
(path F.Cu 20000
1208927 769036
889067 769036
889067 769037
)
)
(wire
(path F.Cu 15238
870000 798400
870000 788103
889067 769037
)
)
(wire
(path F.Cu 15238
1208927 581620
1205100 577793
1205100 575300
)
)
(wire
(path F.Cu 15238
1251600 973500
1251600 929529
)
)
)
(net GND
(wire
(path F.Cu 20000
897207 826443
824970 826443
670000 671473
670000 435400
)
)
(wire
(path F.Cu 20000
897207 826443
1104527 826443
1226200 948116
)
)
(wire
(path F.Cu 20000
897207 816057
897207 826443
)
)
(wire
(path F.Cu 15238
895400 798400
897207 800207
897207 816057
)
)
(wire
(path F.Cu 15238
1226200 948116
1226200 973500
)
)
(wire
(path F.Cu 20000
670000 435400
668555 435400
642308 409153
642308 385925
671949 356284
808268 356284
1001900 549916
)
)
(wire
(path F.Cu 15238
1001900 549916
1001900 575300
)
)
)
(net NET1
(wire
(path F.Cu 20000
837017 790817
825375 790817
720000 685442
720000 422700
)
)
(wire
(path F.Cu 15238
844600 798400
837017 790817
)
)
)
(net NET2
(wire
(path F.Cu 20000
720000 384600
682700 384600
670000 397300
)
)
)
(net SCL
(wire
(path F.Cu 20000
1200800 988622
1213751 1001573
1262669 1001573
1279703 984539
1279703 610226
1216911 547434
1055182 547434
1052700 549916
)
)
(wire
(path F.Cu 15238
1052700 549916
1052700 575300
)
)
(wire
(path F.Cu 15238
1200800 988622
1200800 973500
)
)
)
(net SDA
(wire
(path F.Cu 20000
1027300 549505
1027300 539917
1045031 522186
1227572 522186
1304811 599425
1304811 995273
1272940 1027144
1203241 1027144
1175400 999303
1175400 990546
)
)
(wire
(path F.Cu 15238
1175400 973500
1175400 990546
)
)
(wire
(path F.Cu 15238
1027300 575300
1027300 549505
)
)
)
)
)
)
\ No newline at end of file
#!/usr/bin/env python3
import numpy as np
import ezdxf
import random
from math import sqrt
import copy
class read_old_paperbot():
def __init__(self,dxf_file):
self.dwg=ezdxf.readfile(dxf_file)
self.msp=self.dwg.modelspace()
self.create_layer('Cut',5)
self.create_layer('Fold',4)
# self.create_layer('Pin_temp',6)
self.create_layer('Circuit_Cut',6)
self.create_layer('Circuit_Etc',8)
self.layer_rearrange() ## reagrrange cut and fold lines to corresponding layers
self.remove_wheels() ##remove wheel drawings for this design, no need to call for other designs
self.center_arr=self.find_pin()
# cross_cut(self.msp,2,self.center_arr)
self.savename='dwg_w_layers.dxf'
self.dwg.saveas(self.savename)
def create_layer(self,layer_name,color):
if not layer_name in self.dwg.layers:
self.dwg.layers.new(name=layer_name,dxfattribs={'color':color})
def layer_rearrange(self):
# put fold lines to the new layer 'Fold'
# put cut lines to the new layer 'Cut
for e in self.msp.query('LINE'):
if e.dxf.color!=5:
e.dxf.layer='Fold'
else:
e.dxf.layer='Cut'
def remove_wheels(self):
#no need to call this function for other design
for e in self.msp.query('Arc LINE[layer=="Cut"]'):
if e.dxf.start[0]>=179:
self.msp.delete_entity(e)
def find_pin(self):
tolerance=0.05 #mm
pincutsize_big=3 #mm
pincutsize_small=1 #mm
pin_edge_arr=np.array([[0,0],[0,0]]).reshape(1,2,2)
center_arr=np.array([[0,0]])
for e in self.msp.query('LINE[layer=="Cut"]'):
length= sqrt((e.dxf.start[0]-e.dxf.end[0])**2+(e.dxf.start[1]-e.dxf.end[1])**2)
if length > pincutsize_small-tolerance and length < pincutsize_big + tolerance:
# e.dxf.layer='Pin_temp'
self.msp.delete_entity(e) #08/13/2019 remove all pins in mechanical desing
if e.dxf.start[1]==e.dxf.end[1]: ##this line is horizontal
pin_edge=np.array([e.dxf.start,e.dxf.end])[:,:2]
pin_edge_arr=np.concatenate((pin_edge_arr,pin_edge.reshape(1,2,2)),axis=0)
pin_edge_arr=pin_edge_arr[1:]
# print(pin_edge_arr)
for i in range(len(pin_edge_arr)):
for e in np.delete(pin_edge_arr,i,axis=0):
if pin_edge_arr[i][0,1]-e[0,1]==1.0:
center_x=pin_edge_arr[i][0,0]-0.5
center_y=pin_edge_arr[i][0,1]-0.5
center=np.array([center_x,center_y]).reshape(1,2)
center_arr=np.append(center_arr,center,axis=0)
center_arr=np.unique(center_arr,axis=0)
center_arr=center_arr[1:]
return center_arr
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#!/usr/bin/env python3
def roco_add_ee(me_drawing,netlist_csv,module_libpath,dsnwritier_dir,
trace_width=2,iso_size=2,cross_size=0.66):
"""
This module call script 'roco_dsn.py' to generate a DSN file for auto_router.
An interface will pop up for the user to confirm wiring design,
if a user does not want to change anything, one can just simply close the window.
Routing information will be stored automatically in the same directory.
The routing information will be read and draw the corresponding line on the dxf file
(Please make sure the ME drawing has everything need to cut (obstacles) in "Cut" layer)
Tested Python Version: 3.6
path information needed:
- mechanical design drawing file
- A csv file describes your netlist
- modules library dir
- dsnwritier(sesreader) dir
"""
##########general lib############
import sys
import subprocess
import os
sys.path.insert(1,dsnwritier_dir)
from sesreader import find_wire
from roco_dsn import brd_design
from ee_dwg_processing import pre_process, post_process
ready_for_autorouter=pre_process(me_drawing) #get dwg_for_autorouter.dxf
ee_design=brd_design(ready_for_autorouter.bry_ind,module_libpath,netlist_csv)#,dwgfile='dwg_for_autorouter_temp.dxf') #get paperbot_ee.dsn
subprocess.call(['java','-jar','freeRouting.jar','-de',ee_design.savename+'.dsn','-white','-s'])
wiring_path=find_wire(ee_design.savename,ee_design.pins_at) #read ses file
post_process(me_drawing,wiring_path,ee_design.pins_at,trace_width,iso_size,cross_size) # draw for fabrication
os.remove(ready_for_autorouter.savename)
os.remove(ee_design.savename+'.dsn')
# os.remove(ee_design.savename+'.ses')
os.remove(ee_design.savename+'.rules')
def test():
from read_old_paperbot import read_old_paperbot
dsnwritier_dir='/home/jingyan/Documents/summer_intern_lemur/roco_electrical/dsn_python'
module_libpath='/home/jingyan/Documents/summer_intern_lemur/roco_electrical/libraries/kicad-ESP8266/ESP8266.pretty/'
dwg_path='/home/jingyan/Documents/summer_intern_lemur/roco_electrical/graph-silhouette.dxf'
net_csv='/home/jingyan/Downloads/moduleList.csv'
old=read_old_paperbot(dwg_path) #get dwg_w_layer.dxf
me_dwg=old.savename
roco_add_ee(me_dwg,net_csv,module_libpath,dsnwritier_dir)
test()
\ No newline at end of file
# Automatic Electromechanical Design System for Foldable Robots
- [Motivation](#motivation)
- [Contribution (this repo)](#contribution)
- [Method](#method)
- [To implement my work](#implement-my-work)
- [Demo Video](#demo)
*This repository shares the code and technical details of the research work only, for more information, please check our [paper](https://drive.google.com/file/d/1Indd-3h5moTxg3azODMNYoxxEPuNbpjI/view?usp=sharing) submitted to ICRA2020 or my [engineering journal](developer_journal.md)*.
This research studies **human computer interaction** in terms of developing a **robot compiler** to create electromechanical design for foldable robots. The work presents an integrated design-to-fabrication method for foldable electromechanical devices that rethinks the merging of mechanical and electrical designs. The mechanical substrate of this device can carry electrical functionality; the electrical circuits are parts of the device body.
## Motivation
Printable or foldable robots are becoming a feasible approach for the goal of building robots rapidly with lower cost. While the threshold of the requirement of knowledge for the design and fabricate foldable robots is a barrier to enable the public to create personalized robots, a system doing electrical and mechanical design from a limited amount of user effort is required. In order to be beneficial to the general public, a long-term goal is to develop a compiler that allows people to create a robot with the desired functions.
## Contribution
This repository presents two software contributions from the technical perspective. For more information of the contribution from the research perspective, please see the paper.
- DFM (design for manufacturing) software package for the fabrication process we developed.
- PCB software package generates electrical routing from board outlines converted from an arbitrary mechanical design.
System Pipeline
![](journal_media/final_pipline.png)
## Method
#### DFM software package
This software package takes the electrical design and the mechanical design of a foldable robot as inputs and outputs such drawing file that makes users ready to proceed the fabrication. We use the 2-D drawing file with extension of `dxf` to represent the electromechanical design of a foldable robot. Such drawing are designed to contain multiple layers meaning different fabrication types.
<img src="journal_media/same_pin_intersect.png" width="800">
The software converts each wiring information into wiring patterns onto the mechanical drawing. The patterns can be tuned through user input. The default wiring pattern turns a single wire in the electrical design to a wider wire with three layers. The reason is to remove extra conductive material during the fabrication when users print such robot on a conductive material.
#### PCB osftware package
This software package takes user input of electrical netlist and mechanical design, outputs an electrical design file with wiring information. We utilize the auto-router [FreeRouting](https://freerouting.org/) to generate wiring information that can be passed to the DFM software package. We use the electrical design file with extension of `dsn` to represent the PCB layout. The package imports the mechanical design from a drawing, treats it as PCB outlines and wiring keepout areas.
<img src="journal_media/fig12-2.png" width="800">
## Implement My Work
#### DFM software package
For testing:
~~~
cd EEME_design
python3 roco_electrical.py
~~~
Call the function `roco_electrical.roco_add_ee` for arbitrary design. Arguments:
- me_drawing: mechanical drawing file (`dxf` file, please make sure everything need to cut is in "Cut" layer)
- CSV file that describes your netlist, one can also change it by modifying the information in `roco_dsn.py`
- Electrical modules footprint library
- The directory of `dsnwriter` package (default under same directory of EEME_design)
- Optional parameters:
- trace_width: width of the wiring pattern
- iso_size: size of the isolation pattern
- cross_size: size of the placement pattern
For fabrication process, please see the paper and demo video.
## Demo
One can find demo viedo [here](https://www.youtube.com/watch?v=SaRiikg01lI)
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