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Commit e4119217 authored by Jingyan Ling's avatar Jingyan Ling
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demo_design

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## ENGINEERING JOURNAL
### Jingyan Ling
### 08/29/2019
- Fixing issues:
- better performance with multiple wires connecting to single pin
- changed a lot details in `drawing_processing` script:
- `pop` for endpoints at each wire will be executed before parallel traces
- `pop` and whether the point is connected to a pin is based a rule more restricted so even the wire does not connect to a pin without 0, 90 or 45 degree, it will still pop correctly
- Complete design for demo that has paperbot with an IMU, a touch sensor connecting to LED and Resistor
- ![](journal_media/demo_design.png)
- Fixing `inkscape` unit and scale issue:
- Save as svg
- Select every entities in the drawing
- Lock the width and height scale
- Times (90/96) to either height or width
### 08/28/2019
- Solving issue:
......
journal_media/demo_design.png

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......@@ -53,7 +53,7 @@ $HANDLING
9
$TDUPDATE
40
2458725.597546296
2458725.645324074
9
$HANDSEED
5
......
......@@ -148,7 +148,7 @@ class post_process():
self.cross_cut_size=cross_size#mm
self.trace_cut_width=0.25 #mm
self.convert_unitfrom_ses()
self.draw_wires()
## flatten pin_at_array
self.pin_at=[]
......@@ -157,9 +157,7 @@ class post_process():
self.pin_at.append(pin)
self.remove_redun_wire(0.4)
print(self.wiring)
self.modify_wire_and_merge()
print(self.wiring)
if not self.cross_cut_size==0:
self.draw_cross_cut(self.cross_cut_size)
......@@ -172,7 +170,7 @@ class post_process():
raise Exception ('Isolation box size is required as long as trace width is not equal to zero')
else:
self.draw_complete_traces()
self.draw_wires()
self.draw_rest_iso(self.iso_size,self.trace_cut_width)
self.dwg.saveas('dwg_w_circuit.dxf')
......@@ -227,12 +225,20 @@ class post_process():
endpoints=[path[0],path[-1]]
for j in range(len(endpoints)):
ept=endpoints[j]
if j==1:k=-1
else:k=0
if j==1:
k=-1
kk=-2
else:
k=0
kk=1
further_ept=path[kk]
for pin in self.pin_at:
if distance_between_pts(ept,pin)<=(self.iso_size/2)*sqrt(2):
if point_within_pinbox(ept,pin,self.iso_size):
self.wiring[i][k]=pin
if point_within_pinbox(further_ept,pin,self.iso_size):
self.wiring[i].pop(kk)
break
path_list=copy.deepcopy(self.wiring)
self.wiring=[]
while len(path_list)!=0:
......@@ -370,51 +376,6 @@ class post_process():
path_cp=copy.deepcopy(path)
constrain_s,constrain_e=True,True
# pop and constrain
if [path_index,0] in self.path_at_pin:
connect_index=self.path_at_pin.index([path_index,0])
pin=self.connected_pins[connect_index]
if not distance_between_pts(path[0],pin)==0:
constrain_s=False
warnings.warn('Found wire endpoint not connected to pin exactly, check wire modify in post-process if error')
pop_flag=True
lt=find_line_eq(path[0],path[1])
iso_l_pts=isolation_box_linepts(self.iso_size,pin)
for l_pts in iso_l_pts:
pt1=l_pts[0]
pt2=l_pts[1]
l=find_line_eq(pt1,pt2)
inter=find_intersect(l,lt)
if type(inter)!=type(None) and if_pts_on_interval(inter,path[0],path[1]):
pop_flag=False
break
if pop_flag:
path.pop(1)
# constrain_s=False
if [path_index,-1] in self.path_at_pin:
connect_index=self.path_at_pin.index([path_index,-1])
pin=self.connected_pins[connect_index]
if not distance_between_pts(path[-1],pin)==0:
constrain_e=False
warnings.warn('Found wire endpoint not connected to pin exactly, check wire modify in post-process if error')
if len(path)>2:
pop_flag=True
lt=find_line_eq(path[-1],path[-2])
iso_l_pts=isolation_box_linepts(self.iso_size,pin)
for l_pts in iso_l_pts:
pt1=l_pts[0]
pt2=l_pts[1]
l=find_line_eq(pt1,pt2)
inter=find_intersect(l,lt)
if type(inter)!=type(None) and if_pts_on_interval(inter,path[-1],path[-2]):
pop_flag=False
break
if pop_flag:
path.pop(-2)
if len(path)==1:
continue
######
......@@ -865,5 +826,19 @@ def three_ptw_on_one_line(pt1,pt2,pt3):
if if_pts_on_line(l1,pt3):
return True
def point_within_pinbox(pt,pin,box_size):
"""
pt=further point
pin= pin_location
"""
x,y=pt[0],pt[1]
size=box_size/2
xmin=pin[0]-size
xmax=pin[0]+size
ymin=pin[1]-size
ymax=pin[1]+size
if x>xmin and x<xmax and y>ymin and y<ymax:
return True
else: return False
This diff is collapsed.
(rules PCB paperbot_ee
(snap_angle
fortyfive_degree
)
(autoroute_settings
(fanout off)
(autoroute on)
(postroute on)
(vias on)
(via_costs 50)
(plane_via_costs 5)
(start_ripup_costs 100)
(start_pass_no 60)
(layer_rule F.Cu
(active on)
(preferred_direction vertical)
(preferred_direction_trace_costs 1.0)
(against_preferred_direction_trace_costs 2.3)
)
)
(rule
(width 2000.0)
(clear 200.0)
(clear 125.0 (type smd_to_turn_gap))
(clear 1000.2 (type default_smd))
(clear 1000.0 (type smd_smd))
)
(via_rule
default
)
(class default
3v3 GND NET1 NET2 SCL SDA
(clearance_class default)
(via_rule default)
(rule
(width 2000.0)
)
(circuit
(use_layer F.Cu)
)
)
)
\ No newline at end of file
......@@ -32,87 +32,76 @@
(network_out
(net 3v3
(wire
(path F.Cu 20000
1207429 826494
872710 826494
870000 823784
)
)
(wire
(path F.Cu 20000
1253824 971276
1253824 872889
1207429 826494
)
)
(wire
(path F.Cu 20000
1205100 565218
1205101 565218
1207429 567546
1207429 826494
(path F.Cu 15238
1095538 750926
1205100 641363
1205100 575300
)
)
(wire
(path F.Cu 15238
870000 823784
870000 798400
870000 808782
885189 823971
1022492 823971
1095538 750926
)
)
(wire
(path F.Cu 15238
1205100 565218
1205100 575300
(path F.Cu 20000
1251600 945976
1251600 906988
1095538 750926
)
)
(wire
(path F.Cu 15238
1253824 971276
1251600 973500
1251600 945976
)
)
)
(net GND
(wire
(path F.Cu 20000
1226200 956878
1191566 922244
936727 922244
837766 823283
837766 805234
804441 805234
670000 670793
670000 435400
)
)
(wire
(path F.Cu 20000
670000 435400
670000 662768
812466 805234
837766 805234
)
)
(wire
(path F.Cu 15238
1226200 956878
1226200 973500
837766 809363
966519 938116
1212735 938116
1226200 951581
)
)
(wire
(path F.Cu 20000
1001900 558678
799944 356722
670883 356722
642357 385248
642357 409364
668393 435400
670000 435400
668570 435400
642254 409084
642254 385621
671591 356284
808268 356284
1001900 549916
)
)
(wire
(path F.Cu 15238
1001900 558678
1001900 549916
1001900 575300
)
)
(wire
(path F.Cu 15238
1226200 951581
1226200 973500
)
)
(wire
(path F.Cu 15238
837766 805234
......@@ -123,12 +112,12 @@
(net NET1
(wire
(path F.Cu 20000
720000 422700
720000 681209
801893 763102
873853 763102
897624 786873
897624 796176
897624 786640
881379 770395
805231 770395
720000 685164
720000 422700
)
)
(wire
......@@ -149,55 +138,60 @@
)
(net SCL
(wire
(path F.Cu 15238
1052700 549916
1052700 575300
(path F.Cu 20000
1205645 993546
1200800 988701
)
)
(wire
(path F.Cu 20000
1200800 990122
1212083 1001405
1263132 1001405
1279548 984989
1279548 607923
1214718 543093
1059523 543093
1052700 549916
1052700 561509
1066737 547472
1216392 547472
1279223 610303
1279223 984942
1263042 1001123
1213222 1001123
1205645 993546
)
)
(wire
(path F.Cu 15238
1200800 990122
1200800 973500
1200800 988701
)
)
(wire
(path F.Cu 15238
1052700 575300
1052700 561509
)
)
)
(net SDA
(wire
(path F.Cu 20000
1027300 559154
1027300 543297
1049610 520987
1224236 520987
1302018 598769
1302018 994154
1272397 1023775
1203172 1023775
1175400 996003
1175400 987696
1027300 549916
1055324 521892
1226301 521892
1304527 600118
1304527 994994
1272595 1026926
1203255 1026926
1175400 999071
1175400 988622
)
)
(wire
(path F.Cu 15238
1175400 973500
1175400 987696
1027300 549916
1027300 575300
)
)
(wire
(path F.Cu 15238
1027300 575300
1027300 559154
1175400 988622
1175400 973500
)
)
)
......
......@@ -34,7 +34,7 @@ class brd_design():
# ]
self.netclass_list=[
['default',['3v3','GND','NET1','NET2','SCL','SDA'],'',2000,200]
['default',['3v3','GND','NET1','NET2','SCL','SDA'],'',2000,500]
]
# self.module_list,self.netlist,self.netclass_list=self.read_from_csv(netlist_csv)
......
......@@ -31,14 +31,14 @@ def roco_add_ee(me_drawing,netlist_csv,module_libpath,dsnwritier_dir,
ready_for_autorouter=pre_process(me_drawing) #get dwg_for_autorouter.dxf
ee_design=brd_design(ready_for_autorouter.bry_ind,module_libpath,netlist_csv)#,dwgfile='dwg_for_autorouter_temp.dxf') #get paperbot_ee.dsn
# subprocess.call(['java','-jar','freeRouting.jar','-de',ee_design.savename+'.dsn','-white','-s'])
subprocess.call(['java','-jar','freeRouting.jar','-de',ee_design.savename+'.dsn','-white','-s'])
wiring_path=find_wire(ee_design.savename,ee_design.pins_at) #read ses file
post_process(me_drawing,wiring_path,ee_design.pins_at,trace_width,iso_size,cross_size) # draw for fabrication
# os.remove(ready_for_autorouter.savename)
# os.remove(ee_design.savename+'.dsn')
os.remove(ready_for_autorouter.savename)
os.remove(ee_design.savename+'.dsn')
# os.remove(ee_design.savename+'.ses')
# os.remove(ee_design.savename+'.rules')
os.remove(ee_design.savename+'.rules')
def test():
from read_old_paperbot import read_old_paperbot
......
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