Skip to content
Snippets Groups Projects
Commit beca6536 authored by Jingyan Ling's avatar Jingyan Ling
Browse files

trace+iso tesing

parent d569986c
Branches
No related merge requests found
Showing
with 1925 additions and 19051 deletions
......@@ -5,6 +5,21 @@
- Rearrange the package and draw the path directly on original drawing from old roco
- drawing structure:
- ![](journal_media/dwg_structure.png)
- dsn module placement match:
- instead of getting pin locations from old roco. set pin location based on footprint when user place modules
- Reason:
- 1. no mechanical design needed for pins (especial will turn it to cross cut anyway)
- 2. make sure the electrical board design and drawings will be consistent
- 3. easier to do drawing post processing (dealing with traces and isolation boxes)
- Completed: a cross cut will be drawn at pin locations and that is automatically read from circuit design. The package will only need to load module once when design circuit
- ![](journal_media/auto_read_and_cut.png)
- Draw isolation boxes and connect one edge with parallel traces without causing open circuit (fail)
- ![](journal_media/iso_trace_connect_fail.png)
- TODO:
- Connect traces to isoloation box
- Merge pre-processing code
- Demo
### 08/12/2019
- Finally figure out geometry algorithm on paper
- Coding for parallel trace in following steps:
......
journal_media/auto_read_and_cut.png

28.4 KiB

journal_media/iso_trace_connect_fail.png

43.1 KiB

No preview for this file type
No preview for this file type
No preview for this file type
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
......@@ -21,6 +21,7 @@ dwg_path='/home/jingyan/Documents/summer_intern_lemur/roco_electrical/graph-silh
##########general lib############
import sys
import subprocess
import os
sys.path.insert(1,dsnwritier_dir)
from sesreader import *
from roco_ee_dwg_processing import pre_process, post_process
......@@ -34,4 +35,9 @@ ready_for_autorouter=pre_process(old.savename) #get dwg_for_autorouter.dxf
ee_design=brd_design(0,module_libpath,dwgfile='dwg_for_autorouter_temp.dxf') #get paperbot_ee.dsn
subprocess.call(['java','-jar','freeRouting.jar','-de',ee_design.savename+'.dsn','-white','-s'])
wiring_path=find_wire(ee_design.savename) #read ses file
post_process(old.savename,wiring_path) # draw for fabrication
post_process(old.savename,wiring_path,ee_design.pins_at) # draw for fabrication
os.remove(old.savename)
os.remove(ready_for_autorouter.savename)
os.remove(ee_design.savename+'.dsn')
os.remove(ee_design.savename+'.ses')
\ No newline at end of file
......@@ -6,6 +6,7 @@ import dsnwritier
class brd_design():
def __init__(self,boundary_inx,libpath,savename='paperbot_ee',dwgfile='dwg_for_autorouter.dxf'):
print('generating board desng file (dsn) ......')
self.dwgfile=dwgfile
self.boundary_inx=boundary_inx
self.libpath=libpath
......@@ -31,6 +32,7 @@ class brd_design():
self.net,self.netclass=self.create_net()
self.write_dsn()
self.get_pin_loc()
def brd_general(self):
self.brd=dsnwritier.Dsn()
......@@ -111,6 +113,32 @@ class brd_design():
self.brd.net=self.net
self.brd.netclass=self.netclass
self.brd.to_file(self.savename)
print('dsn file generated.....')
def get_pin_loc(self):
from pykicad.module import Module as mod
import numpy as np
from math import sqrt
self.pins_at=[]
for img in self.module_list:
module=mod.from_file(self.libpath+img[0])
pin_at_arr=[]
module_at=np.array([img[2][0],-img[2][1]])/1000
orientation=360-img[3]
for i in range(len(module.pads)):
pad=module.pads[i]
pin_at_relative=np.array(pad.at) ##mm
if orientation!=0:
x,y=pin_at_relative[0],pin_at_relative[1]
theta=orientation/180*np.pi
x_=x*np.cos(theta)-y*np.sin(theta)
y_=y*np.cos(theta)+x*np.sin(theta)
pin_at_relative=np.array([x_,y_])
pin_at_abs=list(pin_at_relative+module_at)
pin_at_arr.append(pin_at_abs)
self.pins_at.append(pin_at_arr)
# libpath='/home/jingyan/Documents/summer_intern_lemur/roco_electrical/libraries/kicad-ESP8266/ESP8266.pretty/'
......
This diff is collapsed.
......@@ -11,7 +11,7 @@
(via_costs 50)
(plane_via_costs 5)
(start_ripup_costs 100)
(start_pass_no 104)
(start_pass_no 71)
(layer_rule F.Cu
(active on)
(preferred_direction vertical)
......
(session paperbot_ee.ses
(base_design paperbot_ee.dsn)
(placement
(resolution um 10)
(component J1
(place J1 1030000 -880000 front 270)
)
(component U1
(place U1 1030000 -480000 front 90)
)
)
(was_is
)
(routes
(resolution um 10)
(parser
(host_cad "KiCad's Pcbnew")
(host_version "5.1.3-ffb9f22~84~ubuntu18.04.1")
)
(library_out
)
(network_out
(net 3v3
(wire
(path F.Cu 10000
1131600 -816500
1131600 -694273
1066334 -629007
918657 -629007
890300 -600650
)
)
)
(net NET1
(wire
(path F.Cu 10000
864900 -600650
914245 -649995
1070350 -649995
1086128 -665773
1086128 -760372
1030000 -816500
)
)
)
)
)
)
\ No newline at end of file
......@@ -46,14 +46,16 @@ class read_old_paperbot():
def find_pin(self):
tolerance=0.05 #mm
pincutsize=1 #mm
pincutsize_big=3 #mm
pincutsize_small=1 #mm
pin_edge_arr=np.array([[0,0],[0,0]]).reshape(1,2,2)
center_arr=np.array([[0,0]])
for e in self.msp.query('LINE[layer=="Cut"]'):
length= sqrt((e.dxf.start[0]-e.dxf.end[0])**2+(e.dxf.start[1]-e.dxf.end[1])**2)
if length > pincutsize-tolerance and length < pincutsize + tolerance:
if length > pincutsize_small-tolerance and length < pincutsize_big + tolerance:
e.dxf.layer='Pin_temp'
self.msp.delete_entity(e) #08/13/2019 remove all pins in mechanical desing
if e.dxf.start[1]==e.dxf.end[1]: ##this line is horizontal
pin_edge=np.array([e.dxf.start,e.dxf.end])[:,:2]
pin_edge_arr=np.concatenate((pin_edge_arr,pin_edge.reshape(1,2,2)),axis=0)
......
This diff is collapsed.
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment