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Commit 1df770c2 authored by Jingyan Ling's avatar Jingyan Ling
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update journal

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## ENGINEERING JOURNAL ## ENGINEERING JOURNAL
### Jingyan Ling ### Jingyan Ling
### 08/14/2019
- Preparing software demo
- High level of whole project package
- ![](journal_media/roco_ee_highlvl.png)
- Pipeline of drawing changes
- ![](journal_media/dwg_structure.png)
- Package module and classes breakdown
- ![](journal_media/package_support.png)
- Structure of customized package `dsnwriter`
- ![](journal_media/dsnwriter_structure.png)
- Structure of customized package `roco_ee_dwg`
- ![](journal_media/roco_ee_dwg_structure.png)
- Demo Video at [here](https://youtu.be/HeBw4uW3Xzc)
- Solving issue: Connection between isolation box and parallel traces
### 08/13/2019 ### 08/13/2019
- Rearrange the package and draw the path directly on original drawing from old roco - Rearrange the package and draw the path directly on original drawing from old roco
- drawing structure:
- ![](journal_media/dwg_structure.png)
- dsn module placement match: - dsn module placement match:
- instead of getting pin locations from old roco. set pin location based on footprint when user place modules - instead of getting pin locations from old roco. set pin location based on footprint when user place modules
- Reason: - Reason:
- 1. no mechanical design needed for pins (especial will turn it to cross cut anyway) - 1. no mechanical design needed for pins (especial will turn it to cross cut anyway)
- 2. make sure the electrical board design and drawings will be consistent - 2. make sure the electrical board design and drawings will always be consistent
- 3. easier to do drawing post processing (dealing with traces and isolation boxes) - 3. easier to add new electrical components
- 4. easier to do drawing post processing (dealing with traces and isolation boxes)
- Completed: a cross cut will be drawn at pin locations and that is automatically read from circuit design. The package will only need to load module once when design circuit - Completed: a cross cut will be drawn at pin locations and that is automatically read from circuit design. The package will only need to load module once when design circuit
- ![](journal_media/auto_read_and_cut.png) - ![](journal_media/auto_read_and_cut.png)
- Draw isolation boxes and connect one edge with parallel traces without causing open circuit (fail) - Draw isolation boxes and connect one edge with parallel traces without causing open circuit (fail)
...@@ -21,6 +37,8 @@ ...@@ -21,6 +37,8 @@
- Merge pre-processing code - Merge pre-processing code
- Demo - Demo
### 08/12/2019 ### 08/12/2019
- Finally figure out geometry algorithm on paper - Finally figure out geometry algorithm on paper
- Coding for parallel trace in following steps: - Coding for parallel trace in following steps:
......
journal_media/dsnwriter_structure.png

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journal_media/dwg_structure.png

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journal_media/dwg_structure.png

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journal_media/dwg_structure.png
journal_media/dwg_structure.png
journal_media/dwg_structure.png
journal_media/dwg_structure.png
  • 2-up
  • Swipe
  • Onion skin
journal_media/package_support.png

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journal_media/roco_ee_dwg_structure.png

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journal_media/roco_ee_highlvl.png

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...@@ -18,8 +18,8 @@ class brd_design(): ...@@ -18,8 +18,8 @@ class brd_design():
] ]
self.netlist=[ self.netlist=[
['3v3',['U1-3','J1-1']], ['3v3',['U1-3','J1-1']],
['VIN',['U1-1']], ['VIN',['U1-1','J1-6','J1-4']],
['NET1',['U1-2','J1-5']] ['NET1',['U1-2','J1-5','U1-4']]
] ]
self.netclass_list=[ self.netclass_list=[
['default',['3v3','VIN','NET1'],'',1000,200] ['default',['3v3','VIN','NET1'],'',1000,200]
......
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
(via_costs 50) (via_costs 50)
(plane_via_costs 5) (plane_via_costs 5)
(start_ripup_costs 100) (start_ripup_costs 100)
(start_pass_no 71) (start_pass_no 126)
(layer_rule F.Cu (layer_rule F.Cu
(active on) (active on)
(preferred_direction vertical) (preferred_direction vertical)
......
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