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Jingyan Ling's avatar
Jingyan Ling authored
b7769c17
Forked from rocoelec / rocoelectrical
12 commits behind the upstream repository.
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actual_connection_cut.JPG
attempt1_3d.png
attempt2_3d.png
attempt3_2d.png
attempt3_3d.png
attempt4_2d.png
attempt4_3d.png
attempt4_router.png
attempt5_2d.png
attempt5_3d.png
attempt5_router.png
auto_read_and_cut.png
auto_router.gif
auto_router_from_dsn.gif
autorouter_ignore_cu_layer.png
autorouter_w_clearance.png
branch_fix.png
branch_issue.png
circuit_demo.png
circuit_inautorouter.png
compare_dwg_autorouter.png
connected_pin_issue.png
connection_approaches.png
contriA1.png
contriB1.png
contriC1.png
contriD1.png
cross_bug_report.png
cross_cut.png
current_demo.png
cutoncopper_layer.png
demo_design.png
dotnetfile.png
draw_on_dxf_fromses.png
dsnwriter_structure.png
dwg_structure.png
dxf_circuit.png
dxf_import_kicad.png
dxf_importer_code.png
dxf_in_freerouting.png
fab_process.png
fab_result.png
fail_dsn.png
fully_folded_paperbot.png
import_script.png
internal_cut_marked.png
iso_para_done.png
iso_trace_connect_fail.png
iso_with_para.png
isolation_circuit.gif
isolation_circuit.png
issue_solved828.png
keepout_load.png
learning_episodes.gif
lib_toplevel_class.png
manual_dsn.png
matrix_to_img.png
module_dsn.png
module_load_from_lib.png
onshape_dxf_unit.png
package_function.png
package_support.png
paper_outline1.png
parallel_trace.png
parallel_trace_error.png
path_fail.gif
path_learning.gif
pop_inter_issue.png
roco_ee_demo1.mp4
roco_ee_dwg_structure.png
roco_ee_highlvl.png
routing_on_drawing.png
same_pin_intersect.png
sample_autorouting.gif
sample_conn_pcbnew.png
sample_routed.png
schematic_script.png
show_nothing_strokeeveryline.png
show_nothing_strokewithalargerboundary.png
test_before_fullyfold.png
use_dsn_inroco.png
wider_wire.png
zero_width_wire.png