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Commit ce7e9001 authored by Jingyan Ling's avatar Jingyan Ling
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update lib code

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......@@ -384,6 +384,9 @@
- Draw lines directly in `pcbnew` by using line information in `dxf`
- Create a python script serving as Python API by drawing everything on `pcbnew`
- Dependencies:
- ezdxf
- pykicad
- Successfully import `dxf` as outlines from script
- ![](journal_media/import_script.png)
......@@ -399,4 +402,43 @@
- Potential Solutions:
- 1. Explore existing supported export API, and see if modification can be made based on existing API structure
- 2. Learn `dsn` file specification and python library to generate `dsn` file based on design information
\ No newline at end of file
- 2. Learn `dsn` file specification and python library to generate `dsn` file based on design information
### 07/24/2019
- Pipeline change: (skipping `KiCAD`)
- Use (`dxf`+ `pretty` (footprint library) + `net` information ) to generate `dsn` file
- Send `dsn` file to auto-router, save as new `dsn` file
- Read `dsn` file `wiring` information and draw it back on `dxf`
- Analysis on `dsn` file format:
~~~
|--pcb
| |--parser
| |--resolution
| |--unit
| |--structure
| | |--layer 1
| | |-- ...
| | |--boundary
| | |--keepout 1
| | |-- ...
| | |--via
| | |--rule
| |--placement
| | |--component 1
| | |-- ...
| |--library
| | |--image [ref**] 1
| | | |--outline
| | | |--pin
| | |-- ...
| | |--padstack
| | |--...
| |--network
| | |--net [name] 1
| | | |--pins
| | |-- ...
| |--wiring
| | |--wire
~~~
\ No newline at end of file
File added
File added
File added
#!/usr/bin/env python3
from pykicad.sexpr import *
class Component(AST):
tag='component'
schema={
'0':{
'_parser':text,
'_attr':'ref1',
# '_multiple':True
},
'place':{
'0':{
'_parser':text,
'_attr':'ref2',
},
'1':{
'_parser':number + number,
'_attr':'at'
},
'2':{
'_parser':text,
'_attr':'flip'
},
'3':{
'_parser':integer,
'_attr':'orientation'
},
'PN':{
'_parser':text,
'_attr':'name'
}
}
}
def __init__(self,ref1,at,ref2=None,flip='front',orientation=0,name=None):
at[1]=-at[1] #flip y for dsn
ref2=ref1
super(Component,self).__init__(ref1=ref1,ref2=ref2,at=at,flip=flip,orientation=orientation,name=name)
class Outline(AST):
tag='outline'
schema={
'0':{
'path signal':{
'0':{
'_parser':integer,
'_attr':'width'
},
'1':{
'_parser':number,
'_attr':'outline_start'
},
'2':{
'_parser':number,
'_attr':'outline_end'
}
}
}
}
def __init__(self,width=None,outline_start=None,outline_end=None):
super(Outline,self).__init__(width=width,outline_start=outline_start,outline_end=outline_end)
class Pin(AST):
tag='pin'
schema={
'0':{
'_parser':text,
'_attr':'pin_type',
},
'1':{
'_parser':integer,
'_attr':'pin_index',
},
'2':{
'_parser':number+number,
'_attr':'pin_at',
}
}
def __init__(self,pin_index=None,pin_at=None,pin_type='Round[A]Pad_1524_um'):
super(Pin,self).__init__(pin_type=pin_type,pin_index=pin_index,pin_at=pin_at)
class Footprint(AST):
tag='image'
schema={
'0':{
'_parser':text,
'_attr':'ref',
},
'outline':{
'_parser':Outline,
'_multiple':True
},
'pin':{
'_parser':Pin,
'_multiple':True
}
}
def __init__(self,ref=None,outline=None,pin=None):
outline=self.init_list(outline,[])
pin=self.init_list(pin,[])
super(Footprint,self).__init__(ref=ref,outline=outline,pin=pin)
# def load_module(file)
\ No newline at end of file
from pykicad.sexpr import *
class Clearance(AST):
tag='clearance'
schema={
'0':{
'_parser':number,
'_attr':'number'
},
'1':{
'type':{
'_parser':text,
'_attr':'typex'
},
'_optional':True
},
}
def __init__(self,number=200.1,typex=None):
super(Clearance,self).__init__(number=number,typex=typex)
class Rule(AST):
tag='rule'
schema={
'0':{
'width':{
'_parser': number
},
},
'1':{
'clearance':{
'_parser':Clearance,
'_multiple':True
},
},
}
def __init__(self,width=250,clearance=None):
clearance=self.init_list(clearance,[])
super(Rule,self).__init__(width=width,clearance=clearance)
\ No newline at end of file
#!/usr/bin/env python3
from pykicad.sexpr import *
from dsn_rule import *
from dsn_module import Component,Footprint
import dsn_module as module
class Parser(AST):
tag = 'parser'
schema = {
'string_quote' : {
'_parser' : text,
'_attr' : 'quote_char'
},
'space_in_quoted_tokens' : {
'_parser': yes_no,
'_attr' : 'tokens_on_off'
},
'host_cad':{
'_parser': text
},
'host_version':{
'_parser':text
}
}
def __init__(self,
quote_char='\"',
tokens_on_off='on',
host_cad= "KiCad's Pcbnew",
host_version="5.1.3-ffb9f22~84~ubuntu18.04.1"):
super(Parser,self).__init__(quote_char=quote_char,
tokens_on_off=tokens_on_off,
host_cad=host_cad,
host_version=host_version)
class Layer(AST):
tag='layer'
schema={
'0':{
'_parser': text,
'_attr': 'name'
},
'type':{
'_parser': Literal('signal') | 'power' | 'mixed' | 'jumper' | 'user',
'_attr': 'typex'
},
'property':{
'index':{
'_parser':text,
'_attr':'index'
},
},
}
index_ctr=0
def __init__(self,name,typex='signal',index=None):
index=Layer.index_ctr
Layer.index_ctr+=1
super(Layer,self).__init__(name=name,typex=typex,index=index)
class Boundary(AST):
tag='boundary'
schema={
'path pcb':{
'0':{
'_parser':integer,
'_attr':'brd_index'
},
'1':{
'_parser': number,
'_attr': 'path'
},
}
}
index_ctr=0
def __init__(self,path,brd_index=None):
brd_index=Boundary.index_ctr
Boundary.index_ctr+=1
super(Boundary,self).__init__(path=path,brd_index=brd_index)
class Keepout(AST):
tag='keepout'
schema={
'0':{
'0':{
'_parser':text,
'_attr':'name'
},
' ':{
'0': {
'_parser':text,
'_attr':'shape'
},
'1':{
'_parser':text,
'_attr':'typex'
},
'2':{
'_parser':integer,
'_attr':'brd_index'
},
'3':{
'_parser': number,
'_attr':'path'
},
},
},
}
def __init__(self,path,name='\"\"',brd_index=0,shape='polygon',typex='signal'):
super(Keepout,self).__init__(path=path,name=name,brd_index=brd_index,shape=shape,typex=typex)
class Dsn(AST):
tag = 'PCB "kicad_board"'
schema = {
'0':{
'parser' : {
'_parser': Parser
},
},
'1':{
'resolution':{
'_parser': text + integer
},
},
'2':{
'unit':{
'_parser': text
},
},
'3':{
'structure':{
'0':{
'layers':{
'_parser':Layer,
'_multiple':True
},
},
'1':{
'boundary':{
'_parser':Boundary,
'_multiple':True
},
},
'2':{
'keepout':{
'_parser': Keepout,
'_multiple': True
},
},
'3':{
'via':{
'_parser': text,
'_attr': 'via_txt'
},
},
'4':{
'rule':{
'_parser': Rule
}
}
},
'_optional':True
},
'4':{
'placement':{
'0':{
'component':{
'_parser':Component,
'_multiple':True
},
},
},
},
'5':{
'library':{
'0':{
'image':{
'_parser': Footprint,
'_multiple': True
},
}
# 'padstack':{
# '_parser':Padstack,
# '_multiple': True
# }
}
}
}
def __init__(self,
resolution=['um',10],
unit='um',
parser=None,
layers=None,
boundary=None,
keepout=None,
via_txt='"Via[0-1]_800:400_um"',
rule=None,
component=None,
image=None
):
layers=self.init_list(layers,[])
parser=self.init_list(parser,[])
boundary=self.init_list(boundary,[])
keepout=self.init_list(keepout,[])
component=self.init_list(component,[])
image=self.init_list(image,[])
super(Dsn,self).__init__(
resolution=resolution,
unit=unit,
parser=parser,
layers=layers,
boundary=boundary,
keepout=keepout,
via_txt=via_txt,
rule=rule,
component=component,
image=image
)
def to_file(self, path):
if not path.endswith('.dsn'):
path += '.dsn'
with open(path, 'w', encoding='utf-8') as f:
f.write(self.to_string())
File added
#!/usr/bin/env python3
import dsnwritier
from pykicad import pcb
test=dsnwritier.Dsn()
###############################################################################
layers=[
dsnwritier.Layer('F.Cu'),
dsnwritier.Layer('B.Cu')
]
bdata=[137735, -31864.8, 165736, -31864.8, 165736, -113335, 137735, -113335,
137735, -113864, 160735, -113864, 160735, -151336, 150736, -151336,
150736, -151865, 160735, -151865, 160735, -211335, 150736, -211335,
150736, -211865, 169735, -211865, 169735, -249335, 96264.4,-249335,
96264.4, -211865, 138264, -211865, 138264, -211335, 37264.4, -211335,
37264.4, -151865, 138264, -151865, 138264, -151336, 87264.4, -151336,
87264.4, -113864, 119265, -113864, 119265, -113335, 264.583, -113335,
264.583, -31864.8, 78264.5, -31864.8, 78264.5, -264.632, 137735, -264.632,
137735, -31864.8]
kdata1=[138725, -221865, 138725, -244336, 150275, -244336, 150275, -221865,
138725, -221865]
kdata2=[98235.3, -224531, 98764.5, -224531, 98764.5, -219905, 103236, -224376,
103236, -236824, 98764.5, -241294, 98764.5, -236669, 98235.3, -236669,
98235.3, -242572, 103610, -237198, 103765, -237198, 103765, -237043,
103874, -236933, 103765, -236824, 103765, -224376, 103874, -224266,
103765, -224157, 103765, -224002, 103610, -224002, 98235.3, -218628,
98235.3, -224531]
#######################################################################################
parsers= dsnwritier.Parser()
boundary=dsnwritier.Boundary(bdata)
keepout=[
dsnwritier.Keepout(kdata1),
dsnwritier.Keepout(kdata2)]
rule=dsnwritier.Rule()
clearance=[
dsnwritier.Clearance(200.1),
dsnwritier.Clearance(200.1,'default_smd'),
dsnwritier.Clearance(50,'smd_smd')]
rule.clearance=clearance
component=[dsnwritier.Component('U1',[103000,48000],name='"DEV"'),
dsnwritier.Component('J1',[103000,48000],name='"DEV"')]
image1_outline=[
dsnwritier.module.Outline(width=120,outline_start=[-7620, 11430],outline_end=[7540, 11430]),
dsnwritier.module.Outline(width=120,outline_start=[-7620, 11430],outline_end=[7540, -13570]),
dsnwritier.module.Outline(width=120,outline_start=[-7620, -13570],outline_end=[-7620, -13570]),
dsnwritier.module.Outline(width=120,outline_start=[-7620, -13570],outline_end=[-7620, 11430])]
# image1_outline=[dsnwritier.module.Outline(120)]
image1_pin=[
dsnwritier.module.Pin(1,[-6350, 10160]),
dsnwritier.module.Pin(2,[-6350, 7620])]
image1=dsnwritier.Footprint('U1',image1_outline,image1_pin)
image=[image1]
########################################################################################
test.parser=parsers
test.layers=layers
test.boundary=boundary
test.keepout=keepout
test.rule=rule
test.component=component
test.image=image
test.to_file('testdsn.dsn')
(PCB "kicad_board"
(parser
(string_quote ")
(space_in_quoted_tokens on)
(host_cad "KiCad's Pcbnew")
(host_version 5.1.3-ffb9f22~84~ubuntu18.04.1))
(resolution um 10)
(unit um)
(structure
(layer F.Cu
(type signal)
(property
(index 0)))
(layer B.Cu
(type signal)
(property
(index 1)))
(boundary
(path pcb 0 137735 -31864.8000000000 165736 -31864.8000000000 165736 -113335 137735 -113335 137735 -113864 160735 -113864 160735 -151336 150736 -151336 150736 -151865 160735 -151865 160735 -211335 150736 -211335 150736 -211865 169735 -211865 169735 -249335 96264.4000000000 -249335 96264.4000000000 -211865 138264 -211865 138264 -211335 37264.4000000000 -211335 37264.4000000000 -151865 138264 -151865 138264 -151336 87264.4000000000 -151336 87264.4000000000 -113864 119265 -113864 119265 -113335 264.5830000000 -113335 264.5830000000 -31864.8000000000 78264.5000000000 -31864.8000000000 78264.5000000000 -264.6320000000 137735 -264.6320000000 137735 -31864.8000000000))
(keepout ""
( polygon signal 0 138725 -221865 138725 -244336 150275 -244336 150275 -221865 138725 -221865))
(keepout ""
( polygon signal 0 98235.3000000000 -224531 98764.5000000000 -224531 98764.5000000000 -219905 103236 -224376 103236 -236824 98764.5000000000 -241294 98764.5000000000 -236669 98235.3000000000 -236669 98235.3000000000 -242572 103610 -237198 103765 -237198 103765 -237043 103874 -236933 103765 -236824 103765 -224376 103874 -224266 103765 -224157 103765 -224002 103610 -224002 98235.3000000000 -218628 98235.3000000000 -224531))
(via "Via[0-1]_800:400_um")
(rule
(width 250)
(clearance 200.1000000000)
(clearance 200.1000000000
(type default_smd))
(clearance 50
(type smd_smd))))
(placement
(component U1
(place U1 103000 -48000 front 0
(PN "DEV")))
(component J1
(place J1 103000 -48000 front 0
(PN "DEV"))))
(library
(image U1
(outline
(path signal 120 -7620 11430 7540 11430))
(outline
(path signal 120 -7620 11430 7540 -13570))
(outline
(path signal 120 -7620 -13570 -7620 -13570))
(outline
(path signal 120 -7620 -13570 -7620 11430))
(pin Round[A]Pad_1524_um 1 -6350 10160)
(pin Round[A]Pad_1524_um 2 -6350 7620))
))
\ No newline at end of file
This diff is collapsed.
(rules PCB kicad_board
(snap_angle
fortyfive_degree
)
(autoroute_settings
(fanout off)
(autoroute on)
(postroute on)
(vias on)
(via_costs 50)
(plane_via_costs 5)
(start_ripup_costs 100)
(start_pass_no 4)
(layer_rule F.Cu
(active on)
(preferred_direction vertical)
(preferred_direction_trace_costs 1.0)
(against_preferred_direction_trace_costs 2.5)
)
(layer_rule B.Cu
(active on)
(preferred_direction horizontal)
(preferred_direction_trace_costs 1.0)
(against_preferred_direction_trace_costs 1.7)
)
)
(rule
(width 1000.0)
(clear 200.2)
(clear 125.0 (type smd_to_turn_gap))
(clear 50.0 (type smd_smd))
)
(padstack "Via[0-1]_800:400_um"
(shape
(circle F.Cu 800.0 0.0 0.0)
)
(shape
(circle B.Cu 800.0 0.0 0.0)
)
(attach off)
)
(via
"Via[0-1]_800:400_um" "Via[0-1]_800:400_um" default
)
(via
"Via[0-1]_800:400_um-kicad_default" "Via[0-1]_800:400_um" default
)
(via_rule
"kicad_default" "Via[0-1]_800:400_um-kicad_default"
)
(via_rule
default "Via[0-1]_800:400_um"
)
(class default
3v3 VIN
(clearance_class default)
(via_rule default)
(rule
(width 1000.0)
)
(circuit
(use_layer F.Cu B.Cu)
)
)
(class "kicad_default"
(clearance_class default)
(via_rule kicad_default)
(rule
(width 250.0)
)
(circuit
(use_layer F.Cu B.Cu)
)
)
)
\ No newline at end of file
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