Skip to content
Snippets Groups Projects
Commit 0154cc9d authored by Jingyan Ling's avatar Jingyan Ling
Browse files

parse wiring info

parent 28dc0952
Branches
No related merge requests found
Showing
with 166 additions and 16 deletions
## ENGINEERING JOURNAL
### Jingyan Ling
### 08/04/2019
### 08/06/2019
- Successfully parse the wiring information from `ses` file to array
- A little "hacky" way, not using any parsing package
- Stands for `ses` file only
-
### 08/05/2019
- Working on parsing routed (wiring section) text information.
- Ref: [pyparsing](https://scipy-cookbook.readthedocs.io/items/Reading_Custom_Text_Files_with_Pyparsing.html)
- Parsing generated `dsn` file back to `DSN` class
- Fail
- Parsing generated `kicad_pcb` file back to `pykicad` package - `pcb` class
- Success
- Working on:
- debug dsn library so it can read file.
- `pykicad` uses `pyparsing` internally
- Rebuild `ses` file schema. Not working well
### 08/01/2019
......
No preview for this file type
File added
......@@ -213,3 +213,6 @@ class Dsn(AST):
with open(path, 'w', encoding='utf-8') as f:
f.write(self.to_string())
@classmethod
def from_file(cls, path):
return cls.parse(open(path, encoding='utf-8').read())
\ No newline at end of file
#!/usr/bin/env python3
def find_wire(file_path):
ses=open(file_path,'r').read().splitlines()
pathsec_list=[]
for i in range(len(ses)):
if 'path' in ses[i]:
for j in range(i,len(ses)):
if ')' in ses[j]:
pathsec=[i,j]
pathsec_list.append(pathsec)
break
path_list=[]
for sec_bry in pathsec_list:
onepath=[]
for j in range(sec_bry[0]+1,sec_bry[1]):
pts_str=ses[j].split()
ptstart=int(pts_str[0])
ptend=int(pts_str[1])
pts=[ptstart,ptend]
onepath.append(pts)
path_list.append(onepath)
return path_list
\ No newline at end of file
%% Cell type:code id: tags:
``` python
ses=open('paperbot_ee.ses','r').read().splitlines()
```
%% Cell type:code id: tags:
``` python
pathsec_list=[]
for i in range(len(ses)):
if 'path' in ses[i]:
for j in range(i,len(ses)):
if ')' in ses[j]:
pathsec=[i,j]
break
```
%% Output
25
31
36
43
%% Cell type:code id: tags:
``` python
```
File added
......@@ -5,4 +5,7 @@ import subprocess
unrouted_dsn_file='paperbot_ee.dsn'
subprocess.call(['java','-jar','freeRouting.jar','-de',unrouted_dsn_file,'-white','-s'])
\ No newline at end of file
subprocess.call(['java','-jar','freeRouting.jar','-de',unrouted_dsn_file,'-white','-s'])
import re
\ No newline at end of file
#!/usr/bin/env python3
"""
This module call script 'paperbot_dsn.py' to generate a DSN file
for auto_router. An interface will pop up for the user to confirm wiring design,
if a user does not want to change anything, one can just simply close the window.
Routing information will be stored automatically in the same directory.
The routing information will be read and draw the corresponding line on the dxf file
path information needed:
- dsnwritier(sesreader) dir
- modules library dir
- mechanical design drawing file
- dsn/ses file name and (optional:dir)
"""
dsnwritier_dir='/home/jingyan/Documents/summer_intern_lemur/roco_electrical/dsn_python'
module_libpath='/home/jingyan/Documents/summer_intern_lemur/roco_electrical/libraries/kicad-ESP8266/ESP8266.pretty/'
dwg_path='/home/jingyan/Documents/summer_intern_lemur/roco_electrical/dsn_line_test.dxf'
dsn_name='paperbot_ee'
import sys
sys.path.insert(1,dsnwritier_dir)
import paperbot_dsn
paperbot_dsn.brd_design(dwg_path,0,module_libpath,dsn_name)
#!/usr/bin/env python3
import sys
sys.path.insert(1,'/home/jingyan/Documents/summer_intern_lemur/roco_electrical/dsn_python')
# import sys
# sys.path.insert(1,'/home/jingyan/Documents/summer_intern_lemur/roco_electrical/dsn_python')
import dsnwritier
class brd_design():
def __init__(self,dwgfile,boundary_inx,libpath):
def __init__(self,dwgfile,boundary_inx,libpath,savename):
self.dwgfile=dwgfile
self.boundary_inx=boundary_inx
self.libpath=libpath
self.savename=savename
self.module_list=[
['mpu-9250.kicad_mod','J1',[103000,88000],270],
['ESP12F-Devkit-V3.kicad_mod','U1',[103000,48000],90],
]
self.netlist=[
['3v3',['U1-3','J1-1']],
['VIN',['U1-1']]
['VIN',['U1-1']],
['NET1',['U1-2','J1-5']]
]
self.netclass_list=[
['default',['3v3','VIN'],'',1000,200]
['default',['3v3','VIN','NET1'],'',1000,200]
]
self.brd_general()
......@@ -108,12 +111,12 @@ class brd_design():
self.brd.net=self.net
self.brd.netclass=self.netclass
self.brd.to_file('paperbot_ee.dsn')
self.brd.to_file(self.savename)
libpath='/home/jingyan/Documents/summer_intern_lemur/roco_electrical/libraries/kicad-ESP8266/ESP8266.pretty/'
dwgfile='/home/jingyan/Documents/summer_intern_lemur/roco_electrical/dsn_line_test.dxf'
a= brd_design(dwgfile,0,libpath)
# libpath='/home/jingyan/Documents/summer_intern_lemur/roco_electrical/libraries/kicad-ESP8266/ESP8266.pretty/'
# dwgfile='/home/jingyan/Documents/summer_intern_lemur/roco_electrical/dsn_line_test.dxf'
# a= brd_design(dwgfile,0,libpath,'paperbot_ee')
......
......@@ -394,7 +394,9 @@
(pins U1-3 J1-1))
(net VIN
(pins U1-1))
(class default 3v3 VIN
(net NET1
(pins U1-2 J1-5))
(class default 3v3 VIN NET1
(circuit
(use_via ""))
(rule
......
......@@ -11,7 +11,7 @@
(via_costs 50)
(plane_via_costs 5)
(start_ripup_costs 100)
(start_pass_no 4)
(start_pass_no 20)
(layer_rule F.Cu
(active on)
(preferred_direction vertical)
......@@ -48,7 +48,7 @@
default
)
(class default
3v3 VIN
3v3 VIN NET1
(clearance_class default)
(via_rule default)
(rule
......
......@@ -23,7 +23,7 @@
(network_out
(net 3v3
(wire
(path B.Cu 10000
(path F.Mask 10000
890300 -600650
918654 -629004
1049358 -629004
......@@ -32,6 +32,18 @@
)
)
)
(net NET1
(wire
(path B.Cu 10000
864900 -600650
916308 -652058
1072390 -652058
1086143 -665811
1086143 -760357
1030000 -816500
)
)
)
)
)
)
\ No newline at end of file
File added
......@@ -115,7 +115,7 @@ class pcb_editor():
lib_path='libraries/kicad-ESP8266'
lib_path='/home/jingyan/Documents/summer_intern_lemur/roco_electrical/libraries/kicad-ESP8266'
# net_generator=schematic(lib_path)
pcb_generator=pcb_editor(lib_path)
File moved
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment