diff --git a/README.md b/README.md
index ec13a1f4c4720405d05e46a7bf2913a7198217a9..3631c274627df621e22d12754e63c3ce7a779be2 100644
--- a/README.md
+++ b/README.md
@@ -384,6 +384,9 @@
- Draw lines directly in `pcbnew` by using line information in `dxf`
- Create a python script serving as Python API by drawing everything on `pcbnew`
+- Dependencies:
+ - ezdxf
+ - pykicad
- Successfully import `dxf` as outlines from script
- 
@@ -399,4 +402,43 @@
- Potential Solutions:
- 1. Explore existing supported export API, and see if modification can be made based on existing API structure
- - 2. Learn `dsn` file specification and python library to generate `dsn` file based on design information
\ No newline at end of file
+ - 2. Learn `dsn` file specification and python library to generate `dsn` file based on design information
+
+### 07/24/2019
+
+- Pipeline change: (skipping `KiCAD`)
+ - Use (`dxf`+ `pretty` (footprint library) + `net` information ) to generate `dsn` file
+ - Send `dsn` file to auto-router, save as new `dsn` file
+ - Read `dsn` file `wiring` information and draw it back on `dxf`
+
+- Analysis on `dsn` file format:
+~~~
+ |--pcb
+ | |--parser
+ | |--resolution
+ | |--unit
+ | |--structure
+ | | |--layer 1
+ | | |-- ...
+ | | |--boundary
+ | | |--keepout 1
+ | | |-- ...
+ | | |--via
+ | | |--rule
+ | |--placement
+ | | |--component 1
+ | | |-- ...
+ | |--library
+ | | |--image [ref**] 1
+ | | | |--outline
+ | | | |--pin
+ | | |-- ...
+ | | |--padstack
+ | | |--...
+ | |--network
+ | | |--net [name] 1
+ | | | |--pins
+ | | |-- ...
+ | |--wiring
+ | | |--wire
+~~~
\ No newline at end of file
diff --git a/dsn_python/__pycache__/dsn_module.cpython-36.pyc b/dsn_python/__pycache__/dsn_module.cpython-36.pyc
new file mode 100644
index 0000000000000000000000000000000000000000..765aff856af9170e04400c4ecb60a3633bba594c
Binary files /dev/null and b/dsn_python/__pycache__/dsn_module.cpython-36.pyc differ
diff --git a/dsn_python/__pycache__/dsn_rule.cpython-36.pyc b/dsn_python/__pycache__/dsn_rule.cpython-36.pyc
new file mode 100644
index 0000000000000000000000000000000000000000..2f388616b908083da37a765322a2ff98fef510cd
Binary files /dev/null and b/dsn_python/__pycache__/dsn_rule.cpython-36.pyc differ
diff --git a/dsn_python/__pycache__/dsnwritier.cpython-36.pyc b/dsn_python/__pycache__/dsnwritier.cpython-36.pyc
new file mode 100644
index 0000000000000000000000000000000000000000..e0f4d92ed1c145a9a3eba0cd9019a8b1c13527ff
Binary files /dev/null and b/dsn_python/__pycache__/dsnwritier.cpython-36.pyc differ
diff --git a/dsn_python/dsn_module.py b/dsn_python/dsn_module.py
new file mode 100644
index 0000000000000000000000000000000000000000..a4bfd5af8e7334856fafb77d4d4340526ac589d8
--- /dev/null
+++ b/dsn_python/dsn_module.py
@@ -0,0 +1,109 @@
+#!/usr/bin/env python3
+from pykicad.sexpr import *
+
+class Component(AST):
+ tag='component'
+ schema={
+ '0':{
+ '_parser':text,
+ '_attr':'ref1',
+ # '_multiple':True
+ },
+ 'place':{
+ '0':{
+ '_parser':text,
+ '_attr':'ref2',
+ },
+ '1':{
+ '_parser':number + number,
+ '_attr':'at'
+ },
+ '2':{
+ '_parser':text,
+ '_attr':'flip'
+ },
+ '3':{
+ '_parser':integer,
+ '_attr':'orientation'
+ },
+ 'PN':{
+ '_parser':text,
+ '_attr':'name'
+ }
+ }
+ }
+ def __init__(self,ref1,at,ref2=None,flip='front',orientation=0,name=None):
+ at[1]=-at[1] #flip y for dsn
+ ref2=ref1
+ super(Component,self).__init__(ref1=ref1,ref2=ref2,at=at,flip=flip,orientation=orientation,name=name)
+
+class Outline(AST):
+ tag='outline'
+ schema={
+ '0':{
+ 'path signal':{
+ '0':{
+ '_parser':integer,
+ '_attr':'width'
+ },
+ '1':{
+ '_parser':number,
+ '_attr':'outline_start'
+ },
+ '2':{
+ '_parser':number,
+ '_attr':'outline_end'
+ }
+ }
+
+ }
+ }
+ def __init__(self,width=None,outline_start=None,outline_end=None):
+ super(Outline,self).__init__(width=width,outline_start=outline_start,outline_end=outline_end)
+
+class Pin(AST):
+ tag='pin'
+ schema={
+ '0':{
+ '_parser':text,
+ '_attr':'pin_type',
+ },
+ '1':{
+ '_parser':integer,
+ '_attr':'pin_index',
+ },
+ '2':{
+ '_parser':number+number,
+ '_attr':'pin_at',
+ }
+ }
+ def __init__(self,pin_index=None,pin_at=None,pin_type='Round[A]Pad_1524_um'):
+ super(Pin,self).__init__(pin_type=pin_type,pin_index=pin_index,pin_at=pin_at)
+
+
+class Footprint(AST):
+ tag='image'
+ schema={
+ '0':{
+ '_parser':text,
+ '_attr':'ref',
+ },
+ 'outline':{
+ '_parser':Outline,
+ '_multiple':True
+ },
+ 'pin':{
+ '_parser':Pin,
+ '_multiple':True
+
+ }
+
+ }
+ def __init__(self,ref=None,outline=None,pin=None):
+ outline=self.init_list(outline,[])
+ pin=self.init_list(pin,[])
+ super(Footprint,self).__init__(ref=ref,outline=outline,pin=pin)
+
+
+
+# def load_module(file)
\ No newline at end of file
diff --git a/dsn_python/dsn_rule.py b/dsn_python/dsn_rule.py
new file mode 100644
index 0000000000000000000000000000000000000000..8af63ef664b635d7f52007ec1f56a0c0cbfa0466
--- /dev/null
+++ b/dsn_python/dsn_rule.py
@@ -0,0 +1,42 @@
+
+
+from pykicad.sexpr import *
+class Clearance(AST):
+ tag='clearance'
+ schema={
+ '0':{
+ '_parser':number,
+ '_attr':'number'
+ },
+ '1':{
+ 'type':{
+ '_parser':text,
+ '_attr':'typex'
+ },
+ '_optional':True
+ },
+ }
+ def __init__(self,number=200.1,typex=None):
+ super(Clearance,self).__init__(number=number,typex=typex)
+
+class Rule(AST):
+ tag='rule'
+ schema={
+ '0':{
+ 'width':{
+ '_parser': number
+ },
+ },
+ '1':{
+ 'clearance':{
+ '_parser':Clearance,
+ '_multiple':True
+ },
+
+ },
+ }
+
+ def __init__(self,width=250,clearance=None):
+ clearance=self.init_list(clearance,[])
+
+ super(Rule,self).__init__(width=width,clearance=clearance)
\ No newline at end of file
diff --git a/dsn_python/dsnwritier.py b/dsn_python/dsnwritier.py
new file mode 100644
index 0000000000000000000000000000000000000000..8a7b15395f5bde1cb172e4f041653a1e57148cc5
--- /dev/null
+++ b/dsn_python/dsnwritier.py
@@ -0,0 +1,243 @@
+#!/usr/bin/env python3
+from pykicad.sexpr import *
+from dsn_rule import *
+from dsn_module import Component,Footprint
+import dsn_module as module
+
+class Parser(AST):
+ tag = 'parser'
+ schema = {
+ 'string_quote' : {
+ '_parser' : text,
+ '_attr' : 'quote_char'
+ },
+ 'space_in_quoted_tokens' : {
+ '_parser': yes_no,
+ '_attr' : 'tokens_on_off'
+ },
+ 'host_cad':{
+ '_parser': text
+ },
+ 'host_version':{
+ '_parser':text
+ }
+ }
+ def __init__(self,
+ quote_char='\"',
+ tokens_on_off='on',
+ host_cad= "KiCad's Pcbnew",
+ host_version="5.1.3-ffb9f22~84~ubuntu18.04.1"):
+
+ super(Parser,self).__init__(quote_char=quote_char,
+ tokens_on_off=tokens_on_off,
+ host_cad=host_cad,
+ host_version=host_version)
+
+
+class Layer(AST):
+ tag='layer'
+ schema={
+ '0':{
+ '_parser': text,
+ '_attr': 'name'
+ },
+ 'type':{
+ '_parser': Literal('signal') | 'power' | 'mixed' | 'jumper' | 'user',
+ '_attr': 'typex'
+ },
+ 'property':{
+ 'index':{
+ '_parser':text,
+ '_attr':'index'
+ },
+ },
+ }
+ index_ctr=0
+
+ def __init__(self,name,typex='signal',index=None):
+ index=Layer.index_ctr
+ Layer.index_ctr+=1
+ super(Layer,self).__init__(name=name,typex=typex,index=index)
+
+
+class Boundary(AST):
+ tag='boundary'
+ schema={
+ 'path pcb':{
+ '0':{
+ '_parser':integer,
+ '_attr':'brd_index'
+ },
+ '1':{
+ '_parser': number,
+ '_attr': 'path'
+ },
+
+ }
+ }
+
+ index_ctr=0
+ def __init__(self,path,brd_index=None):
+ brd_index=Boundary.index_ctr
+ Boundary.index_ctr+=1
+
+ super(Boundary,self).__init__(path=path,brd_index=brd_index)
+
+class Keepout(AST):
+ tag='keepout'
+ schema={
+ '0':{
+ '0':{
+ '_parser':text,
+ '_attr':'name'
+ },
+
+ ' ':{
+ '0': {
+ '_parser':text,
+ '_attr':'shape'
+ },
+ '1':{
+ '_parser':text,
+ '_attr':'typex'
+ },
+ '2':{
+ '_parser':integer,
+ '_attr':'brd_index'
+ },
+ '3':{
+ '_parser': number,
+ '_attr':'path'
+ },
+ },
+ },
+ }
+ def __init__(self,path,name='\"\"',brd_index=0,shape='polygon',typex='signal'):
+
+ super(Keepout,self).__init__(path=path,name=name,brd_index=brd_index,shape=shape,typex=typex)
+
+
+
+class Dsn(AST):
+ tag = 'PCB "kicad_board"'
+ schema = {
+ '0':{
+ 'parser' : {
+ '_parser': Parser
+ },
+ },
+ '1':{
+ 'resolution':{
+ '_parser': text + integer
+ },
+ },
+ '2':{
+ 'unit':{
+ '_parser': text
+ },
+ },
+ '3':{
+ 'structure':{
+ '0':{
+ 'layers':{
+ '_parser':Layer,
+ '_multiple':True
+ },
+ },
+ '1':{
+ 'boundary':{
+ '_parser':Boundary,
+ '_multiple':True
+ },
+ },
+ '2':{
+ 'keepout':{
+ '_parser': Keepout,
+ '_multiple': True
+ },
+ },
+ '3':{
+ 'via':{
+ '_parser': text,
+ '_attr': 'via_txt'
+ },
+ },
+ '4':{
+ 'rule':{
+ '_parser': Rule
+ }
+ }
+ },
+ '_optional':True
+ },
+ '4':{
+ 'placement':{
+ '0':{
+ 'component':{
+ '_parser':Component,
+ '_multiple':True
+ },
+ },
+ },
+ },
+ '5':{
+ 'library':{
+ '0':{
+ 'image':{
+ '_parser': Footprint,
+ '_multiple': True
+ },
+ }
+
+ # 'padstack':{
+ # '_parser':Padstack,
+ # '_multiple': True
+ # }
+
+ }
+ }
+
+
+
+ }
+
+ def __init__(self,
+ resolution=['um',10],
+ unit='um',
+ parser=None,
+ layers=None,
+ boundary=None,
+ keepout=None,
+ via_txt='"Via[0-1]_800:400_um"',
+ rule=None,
+ component=None,
+ image=None
+ ):
+
+ layers=self.init_list(layers,[])
+ parser=self.init_list(parser,[])
+ boundary=self.init_list(boundary,[])
+ keepout=self.init_list(keepout,[])
+ component=self.init_list(component,[])
+ image=self.init_list(image,[])
+
+
+ super(Dsn,self).__init__(
+ resolution=resolution,
+ unit=unit,
+ parser=parser,
+ layers=layers,
+ boundary=boundary,
+ keepout=keepout,
+ via_txt=via_txt,
+ rule=rule,
+ component=component,
+ image=image
+ )
+
+ def to_file(self, path):
+ if not path.endswith('.dsn'):
+ path += '.dsn'
+ with open(path, 'w', encoding='utf-8') as f:
+ f.write(self.to_string())
+
diff --git a/dsn_python/dsnwritier.pyc b/dsn_python/dsnwritier.pyc
new file mode 100644
index 0000000000000000000000000000000000000000..b54d2f136e0a7eed1bceb4c152ea8ba6585e81cf
Binary files /dev/null and b/dsn_python/dsnwritier.pyc differ
diff --git a/dsn_python/test_dsn_python.py b/dsn_python/test_dsn_python.py
new file mode 100644
index 0000000000000000000000000000000000000000..86f6e431478fac39ead12aa1262c9275cd0c95e8
--- /dev/null
+++ b/dsn_python/test_dsn_python.py
@@ -0,0 +1,75 @@
+#!/usr/bin/env python3
+import dsnwritier
+from pykicad import pcb
+
+test=dsnwritier.Dsn()
+
+###############################################################################
+layers=[
+ dsnwritier.Layer('F.Cu'),
+ dsnwritier.Layer('B.Cu')
+]
+
+
+bdata=[137735, -31864.8, 165736, -31864.8, 165736, -113335, 137735, -113335,
+ 137735, -113864, 160735, -113864, 160735, -151336, 150736, -151336,
+ 150736, -151865, 160735, -151865, 160735, -211335, 150736, -211335,
+ 150736, -211865, 169735, -211865, 169735, -249335, 96264.4,-249335,
+ 96264.4, -211865, 138264, -211865, 138264, -211335, 37264.4, -211335,
+ 37264.4, -151865, 138264, -151865, 138264, -151336, 87264.4, -151336,
+ 87264.4, -113864, 119265, -113864, 119265, -113335, 264.583, -113335,
+ 264.583, -31864.8, 78264.5, -31864.8, 78264.5, -264.632, 137735, -264.632,
+ 137735, -31864.8]
+
+kdata1=[138725, -221865, 138725, -244336, 150275, -244336, 150275, -221865,
+ 138725, -221865]
+kdata2=[98235.3, -224531, 98764.5, -224531, 98764.5, -219905, 103236, -224376,
+ 103236, -236824, 98764.5, -241294, 98764.5, -236669, 98235.3, -236669,
+ 98235.3, -242572, 103610, -237198, 103765, -237198, 103765, -237043,
+ 103874, -236933, 103765, -236824, 103765, -224376, 103874, -224266,
+ 103765, -224157, 103765, -224002, 103610, -224002, 98235.3, -218628,
+ 98235.3, -224531]
+
+#######################################################################################
+parsers= dsnwritier.Parser()
+
+boundary=dsnwritier.Boundary(bdata)
+
+keepout=[
+ dsnwritier.Keepout(kdata1),
+ dsnwritier.Keepout(kdata2)]
+
+rule=dsnwritier.Rule()
+clearance=[
+ dsnwritier.Clearance(200.1),
+ dsnwritier.Clearance(200.1,'default_smd'),
+ dsnwritier.Clearance(50,'smd_smd')]
+rule.clearance=clearance
+
+component=[dsnwritier.Component('U1',[103000,48000],name='"DEV"'),
+ dsnwritier.Component('J1',[103000,48000],name='"DEV"')]
+
+
+image1_outline=[
+ dsnwritier.module.Outline(width=120,outline_start=[-7620, 11430],outline_end=[7540, 11430]),
+ dsnwritier.module.Outline(width=120,outline_start=[-7620, 11430],outline_end=[7540, -13570]),
+ dsnwritier.module.Outline(width=120,outline_start=[-7620, -13570],outline_end=[-7620, -13570]),
+ dsnwritier.module.Outline(width=120,outline_start=[-7620, -13570],outline_end=[-7620, 11430])]
+# image1_outline=[dsnwritier.module.Outline(120)]
+image1_pin=[
+ dsnwritier.module.Pin(1,[-6350, 10160]),
+ dsnwritier.module.Pin(2,[-6350, 7620])]
+
+image1=dsnwritier.Footprint('U1',image1_outline,image1_pin)
+image=[image1]
+
+########################################################################################
+test.parser=parsers
+test.layers=layers
+test.boundary=boundary
+test.keepout=keepout
+test.rule=rule
+test.component=component
+test.image=image
+
+test.to_file('testdsn.dsn')
diff --git a/dsn_python/testdsn.dsn b/dsn_python/testdsn.dsn
new file mode 100644
index 0000000000000000000000000000000000000000..14da9ab6b506d80a9a8993b163bfe01890d10c11
--- /dev/null
+++ b/dsn_python/testdsn.dsn
@@ -0,0 +1,52 @@
+
+(PCB "kicad_board"
+(parser
+ (string_quote ")
+ (space_in_quoted_tokens on)
+ (host_cad "KiCad's Pcbnew")
+ (host_version 5.1.3-ffb9f22~84~ubuntu18.04.1))
+ (resolution um 10)
+ (unit um)
+ (structure
+(layer F.Cu
+ (type signal)
+ (property
+ (index 0)))
+(layer B.Cu
+ (type signal)
+ (property
+ (index 1)))
+(boundary
+ (path pcb 0 137735 -31864.8000000000 165736 -31864.8000000000 165736 -113335 137735 -113335 137735 -113864 160735 -113864 160735 -151336 150736 -151336 150736 -151865 160735 -151865 160735 -211335 150736 -211335 150736 -211865 169735 -211865 169735 -249335 96264.4000000000 -249335 96264.4000000000 -211865 138264 -211865 138264 -211335 37264.4000000000 -211335 37264.4000000000 -151865 138264 -151865 138264 -151336 87264.4000000000 -151336 87264.4000000000 -113864 119265 -113864 119265 -113335 264.5830000000 -113335 264.5830000000 -31864.8000000000 78264.5000000000 -31864.8000000000 78264.5000000000 -264.6320000000 137735 -264.6320000000 137735 -31864.8000000000))
+(keepout ""
+ ( polygon signal 0 138725 -221865 138725 -244336 150275 -244336 150275 -221865 138725 -221865))
+(keepout ""
+ ( polygon signal 0 98235.3000000000 -224531 98764.5000000000 -224531 98764.5000000000 -219905 103236 -224376 103236 -236824 98764.5000000000 -241294 98764.5000000000 -236669 98235.3000000000 -236669 98235.3000000000 -242572 103610 -237198 103765 -237198 103765 -237043 103874 -236933 103765 -236824 103765 -224376 103874 -224266 103765 -224157 103765 -224002 103610 -224002 98235.3000000000 -218628 98235.3000000000 -224531))
+ (via "Via[0-1]_800:400_um")
+(rule
+ (width 250)
+(clearance 200.1000000000)
+(clearance 200.1000000000
+ (type default_smd))
+(clearance 50
+ (type smd_smd))))
+ (placement
+(component U1
+ (place U1 103000 -48000 front 0
+ (PN "DEV")))
+(component J1
+ (place J1 103000 -48000 front 0
+ (PN "DEV"))))
+ (library
+(image U1
+(outline
+ (path signal 120 -7620 11430 7540 11430))
+(outline
+ (path signal 120 -7620 11430 7540 -13570))
+(outline
+ (path signal 120 -7620 -13570 -7620 -13570))
+(outline
+ (path signal 120 -7620 -13570 -7620 11430))
+(pin Round[A]Pad_1524_um 1 -6350 10160)
+(pin Round[A]Pad_1524_um 2 -6350 7620))
+))
\ No newline at end of file
diff --git a/kicad_board.dsn b/kicad_board.dsn
index bf4e54d0ef852f78c40625f484795c6a10b6639c..aa33aa96fea71b247d1c4eca49b355e562bf5003 100644
--- a/kicad_board.dsn
+++ b/kicad_board.dsn
@@ -1,1208 +1,249 @@
-
-(PCB "kicad_board"
+(pcb /home/jingyan/Documents/summer_intern_lemur/roco_electrical/kicad_board.dsn
(parser
(string_quote ")
(space_in_quoted_tokens on)
(host_cad "KiCad's Pcbnew")
(host_version "5.1.3-ffb9f22~84~ubuntu18.04.1")
- (generated_by_freeroute)
)
(resolution um 10)
+ (unit um)
(structure
- (boundary
- (rect pcb 164.6 -249435.0 169835.0 -164.6)
- )
- (boundary
- (polygon signal 0
- 96264.4 -249335.0
- 169735.0 -249335.0
- 169735.0 -211865.0
- 150736.0 -211865.0
- 150736.0 -211335.0
- 160735.0 -211335.0
- 160735.0 -151865.0
- 150736.0 -151865.0
- 150736.0 -151336.0
- 160735.0 -151336.0
- 160735.0 -113864.0
- 137735.0 -113864.0
- 137735.0 -113335.0
- 165736.0 -113335.0
- 165736.0 -31864.8
- 137735.0 -31864.8
- 137735.0 -264.6
- 78264.5 -264.6
- 78264.5 -31864.8
- 264.6 -31864.8
- 264.6 -113335.0
- 119265.0 -113335.0
- 119265.0 -113864.0
- 87264.4 -113864.0
- 87264.4 -151336.0
- 138264.0 -151336.0
- 138264.0 -151865.0
- 37264.4 -151865.0
- 37264.4 -211335.0
- 138264.0 -211335.0
- 138264.0 -211865.0
- 96264.4 -211865.0
- )
- )
- (snap_angle
- fortyfive_degree
- )
- (via "Via[0-1]_800:400_um")
- (control
- (via_at_smd off)
- )
- (rule
- (width 1000.0)
- (clear 200.2)
- (clear 125.0 (type smd_to_turn_gap))
- (clear 50.0 (type smd_smd))
- )
(layer F.Cu
(type signal)
+ (property
+ (index 0)
+ )
)
(layer B.Cu
(type signal)
- )
- (autoroute_settings
- (fanout off)
- (autoroute on)
- (postroute on)
- (vias on)
- (via_costs 50)
- (plane_via_costs 5)
- (start_ripup_costs 100)
- (start_pass_no 4)
- (layer_rule F.Cu
- (active on)
- (preferred_direction vertical)
- (preferred_direction_trace_costs 1.0)
- (against_preferred_direction_trace_costs 2.5)
- )
- (layer_rule B.Cu
- (active on)
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- (pin "Round[A]Pad_1524_um" 5 -6350.0 0.0)
- (pin "Round[A]Pad_1524_um" 6 -6350.0 -2540.0)
- (pin "Round[A]Pad_1524_um" 7 -6350.0 -5080.0)
- (pin "Round[A]Pad_1524_um" 8 -6350.0 -7620.0)
- (pin "Round[A]Pad_1524_um" 9 -6350.0 -10160.0)
- (pin "Round[A]Pad_1524_um" 10 -6350.0 -12700.0)
- (outline
- (polygon signal 0
- -7644.9 11370.0
- 7564.9 11370.0
- 7600.0 11405.1
- 7600.0 11454.9
- 7564.9 11490.0
- -7644.9 11490.0
- -7680.0 11454.9
- -7680.0 11405.1
- )
- )
- (outline
- (polygon signal 0
- 7595.1 -13630.0
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- )
- )
- (outline
- (polygon signal 0
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- )
- )
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- (polygon signal 0
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- -7680.0 11454.9
- -7680.0 -13594.9
- )
- )
- )
- (padstack "Round[A]Pad_1524_um"
- (shape
- (circle F.Cu 1524.0 0.0 0.0)
- )
- (shape
- (circle B.Cu 1524.0 0.0 0.0)
- )
+ (outline (path signal 120 -7620 11430 7540 11430))
+ (outline (path signal 120 7620 11430 7620 -13570))
+ (outline (path signal 120 7620 -13570 -7620 -13570))
+ (outline (path signal 120 -7620 -13570 -7620 11430))
+ (pin Round[A]Pad_1524_um 1 -6350 10160)
+ (pin Round[A]Pad_1524_um 2 -6350 7620)
+ (pin Round[A]Pad_1524_um 3 -6350 5080)
+ (pin Round[A]Pad_1524_um 4 -6350 2540)
+ (pin Round[A]Pad_1524_um 5 -6350 0)
+ (pin Round[A]Pad_1524_um 6 -6350 -2540)
+ (pin Round[A]Pad_1524_um 7 -6350 -5080)
+ (pin Round[A]Pad_1524_um 8 -6350 -7620)
+ (pin Round[A]Pad_1524_um 9 -6350 -10160)
+ (pin Round[A]Pad_1524_um 10 -6350 -12700)
+ )
+ (padstack Round[A]Pad_1524_um
+ (shape (circle F.Cu 1524))
+ (shape (circle B.Cu 1524))
(attach off)
)
(padstack "Via[0-1]_800:400_um"
- (shape
- (circle F.Cu 800.0 0.0 0.0)
- )
- (shape
- (circle B.Cu 800.0 0.0 0.0)
- )
+ (shape (circle F.Cu 800))
+ (shape (circle B.Cu 800))
(attach off)
)
)
(network
- (net 3v3 1
- (pins
- J1-1
- U1-3
- )
- )
- (net VIN 1
- (pins
- U1-1
- )
- )
- (via
- "Via[0-1]_800:400_um" "Via[0-1]_800:400_um" default
- )
- (via
- "Via[0-1]_800:400_um-kicad_default" "Via[0-1]_800:400_um" "kicad_default"
+ (net 3v3
+ (pins U1-3 J1-1)
)
- (via_rule
- default "Via[0-1]_800:400_um"
+ (net VIN
+ (pins U1-1)
)
- (via_rule
- "kicad_default" "Via[0-1]_800:400_um-kicad_default"
- )
- (via_rule
- default "Via[0-1]_800:400_um"
- )
- (class default
- 3v3 VIN
- (clearance_class default)
- (via_rule default)
- (rule
- (width 1000.0)
+ (class kicad_default ""
+ (circuit
+ (use_via Via[0-1]_800:400_um)
)
- (circuit
- (use_layer F.Cu B.Cu)
+ (rule
+ (width 250)
+ (clearance 200.1)
)
)
- (class "kicad_default"
- (clearance_class "kicad_default")
- (via_rule kicad_default)
- (rule
- (width 250.0)
+ (class default 3v3 GND VIN
+ (circuit
+ (use_via Via[0-1]_800:400_um)
)
- (circuit
- (use_layer F.Cu B.Cu)
+ (rule
+ (width 1000)
+ (clearance 200.1)
)
)
)
(wiring
- (wire
- (polyline_path B.Cu 1000.0
- 110160.0 -80650.0 110159.9 -80650.0
- 110160.0 -80650.0 110160.0 -68737.2
- 110160.0 -68737.2 104063.6 -62640.8
- 104063.6 -62640.8 89030.0 -62640.8
- 89030.0 -60065.0 89029.9 -60064.9
- 89030.0 -60065.0 89030.1 -60065.0
- )
- (net 3v3 1)
- (clearance_class default)
- )
)
-)
\ No newline at end of file
+)
diff --git a/kicad_board.rules b/kicad_board.rules
deleted file mode 100644
index 35b82c18c777a264f610496af453db96aba066ef..0000000000000000000000000000000000000000
--- a/kicad_board.rules
+++ /dev/null
@@ -1,76 +0,0 @@
-
-(rules PCB kicad_board
- (snap_angle
- fortyfive_degree
- )
- (autoroute_settings
- (fanout off)
- (autoroute on)
- (postroute on)
- (vias on)
- (via_costs 50)
- (plane_via_costs 5)
- (start_ripup_costs 100)
- (start_pass_no 4)
- (layer_rule F.Cu
- (active on)
- (preferred_direction vertical)
- (preferred_direction_trace_costs 1.0)
- (against_preferred_direction_trace_costs 2.5)
- )
- (layer_rule B.Cu
- (active on)
- (preferred_direction horizontal)
- (preferred_direction_trace_costs 1.0)
- (against_preferred_direction_trace_costs 1.7)
- )
- )
- (rule
- (width 1000.0)
- (clear 200.2)
- (clear 125.0 (type smd_to_turn_gap))
- (clear 50.0 (type smd_smd))
- )
- (padstack "Via[0-1]_800:400_um"
- (shape
- (circle F.Cu 800.0 0.0 0.0)
- )
- (shape
- (circle B.Cu 800.0 0.0 0.0)
- )
- (attach off)
- )
- (via
- "Via[0-1]_800:400_um" "Via[0-1]_800:400_um" default
- )
- (via
- "Via[0-1]_800:400_um-kicad_default" "Via[0-1]_800:400_um" default
- )
- (via_rule
- "kicad_default" "Via[0-1]_800:400_um-kicad_default"
- )
- (via_rule
- default "Via[0-1]_800:400_um"
- )
- (class default
- 3v3 VIN
- (clearance_class default)
- (via_rule default)
- (rule
- (width 1000.0)
- )
- (circuit
- (use_layer F.Cu B.Cu)
- )
- )
- (class "kicad_default"
- (clearance_class default)
- (via_rule kicad_default)
- (rule
- (width 250.0)
- )
- (circuit
- (use_layer F.Cu B.Cu)
- )
- )
-)
\ No newline at end of file
diff --git a/kicad_board_routed.dsn b/kicad_board_routed.dsn
new file mode 100644
index 0000000000000000000000000000000000000000..654197b912caa41efea2c3b3e4814c1a5f1b6458
--- /dev/null
+++ b/kicad_board_routed.dsn
@@ -0,0 +1,1234 @@
+
+(PCB "kicad_board"
+ (parser
+ (string_quote ")
+ (space_in_quoted_tokens on)
+ (host_cad "KiCad's Pcbnew")
+ (host_version "5.1.3-ffb9f22~84~ubuntu18.04.1")
+ (generated_by_freeroute)
+ )
+ (resolution um 10)
+ (structure
+ (boundary
+ (rect pcb 164.6 -249435.0 169835.0 -164.6)
+ )
+ (boundary
+ (polygon signal 0
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+ 37264.4 -211335.0
+ 138264.0 -211335.0
+ 138264.0 -211865.0
+ 96264.4 -211865.0
+ )
+ )
+ (snap_angle
+ fortyfive_degree
+ )
+ (via "Via[0-1]_800:400_um")
+ (control
+ (via_at_smd off)
+ )
+ (rule
+ (width 1000.0)
+ (clear 200.2)
+ (clear 125.0 (type smd_to_turn_gap))
+ (clear 50.0 (type smd_smd))
+ )
+ (layer F.Cu
+ (type signal)
+ )
+ (layer B.Cu
+ (type signal)
+ )
+ (autoroute_settings
+ (fanout off)
+ (autoroute on)
+ (postroute on)
+ (vias on)
+ (via_costs 50)
+ (plane_via_costs 5)
+ (start_ripup_costs 100)
+ (start_pass_no 7)
+ (layer_rule F.Cu
+ (active on)
+ (preferred_direction vertical)
+ (preferred_direction_trace_costs 1.0)
+ (against_preferred_direction_trace_costs 2.5)
+ )
+ (layer_rule B.Cu
+ (active on)
+ (preferred_direction horizontal)
+ (preferred_direction_trace_costs 1.0)
+ (against_preferred_direction_trace_costs 1.7)
+ )
+ )
+ (keepout
+ (polygon B.Cu 0
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+ 106265.0 -26735.3
+ 106265.0 -18264.6
+ 110265.0 -18264.6
+ 110265.0 -17735.4
+ 105736.0 -17735.4
+ )
+ (clearance_class default)
+ )
+ (keepout
+ (polygon F.Cu 0
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+ 105736.0 -17735.4
+ )
+ (clearance_class default)
+ )
+ (keepout
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+ )
+ (clearance_class default)
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+ )
+ (clearance_class default)
+ )
+ (keepout
+ (polygon B.Cu 0
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+ )
+ (clearance_class default)
+ )
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+ )
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+ )
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+ )
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+ )
+ (keepout
+ (polygon B.Cu 0
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+ 107485.0 -74585.7
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+ 81014.7 -67114.8
+ )
+ (clearance_class default)
+ )
+ (keepout
+ (polygon F.Cu 0
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+ 107485.0 -74585.7
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+ )
+ (clearance_class default)
+ )
+ (keepout
+ (polygon B.Cu 0
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+ )
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+ )
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+ )
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+ )
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+ -7644.9 11370.0
+ 7564.9 11370.0
+ 7600.0 11405.1
+ 7600.0 11454.9
+ 7564.9 11490.0
+ -7644.9 11490.0
+ -7680.0 11454.9
+ -7680.0 11405.1
+ )
+ )
+ (outline
+ (polygon signal 0
+ 7595.1 -13630.0
+ 7644.9 -13630.0
+ 7680.0 -13594.9
+ 7680.0 11454.9
+ 7644.9 11490.0
+ 7595.1 11490.0
+ 7560.0 11454.9
+ 7560.0 -13594.9
+ )
+ )
+ (outline
+ (polygon signal 0
+ -7644.9 -13630.0
+ 7644.9 -13630.0
+ 7680.0 -13594.9
+ 7680.0 -13545.1
+ 7644.9 -13510.0
+ -7644.9 -13510.0
+ -7680.0 -13545.1
+ -7680.0 -13594.9
+ )
+ )
+ (outline
+ (polygon signal 0
+ -7644.9 -13630.0
+ -7595.1 -13630.0
+ -7560.0 -13594.9
+ -7560.0 11454.9
+ -7595.1 11490.0
+ -7644.9 11490.0
+ -7680.0 11454.9
+ -7680.0 -13594.9
+ )
+ )
+ )
+ (padstack "Round[A]Pad_1524_um"
+ (shape
+ (circle F.Cu 1524.0 0.0 0.0)
+ )
+ (shape
+ (circle B.Cu 1524.0 0.0 0.0)
+ )
+ (attach off)
+ )
+ (padstack "Via[0-1]_800:400_um"
+ (shape
+ (circle F.Cu 800.0 0.0 0.0)
+ )
+ (shape
+ (circle B.Cu 800.0 0.0 0.0)
+ )
+ (attach off)
+ )
+ )
+ (network
+ (net 3v3 1
+ (pins
+ J1-1
+ U1-3
+ )
+ )
+ (net VIN 1
+ (pins
+ U1-1
+ )
+ )
+ (via
+ "Via[0-1]_800:400_um" "Via[0-1]_800:400_um" default
+ )
+ (via
+ "Via[0-1]_800:400_um-kicad_default" "Via[0-1]_800:400_um" default
+ )
+ (via_rule
+ default "Via[0-1]_800:400_um"
+ )
+ (via_rule
+ "kicad_default" "Via[0-1]_800:400_um-kicad_default"
+ )
+ (via_rule
+ default "Via[0-1]_800:400_um"
+ )
+ (class default
+ 3v3 VIN
+ (clearance_class default)
+ (via_rule default)
+ (rule
+ (width 1000.0)
+ )
+ (circuit
+ (use_layer F.Cu B.Cu)
+ )
+ )
+ (class "kicad_default"
+ (clearance_class default)
+ (via_rule kicad_default)
+ (rule
+ (width 250.0)
+ )
+ (circuit
+ (use_layer F.Cu B.Cu)
+ )
+ )
+ )
+ (wiring
+ (wire
+ (polyline_path B.Cu 1000.0
+ 110160.0 -80650.0 110159.9 -80650.0
+ 110160.0 -80650.0 110160.0 -68737.2
+ 110160.0 -68737.2 104063.6 -62640.8
+ 104063.6 -62640.8 89030.0 -62640.8
+ 89030.0 -60065.0 89029.9 -60064.9
+ 89030.0 -60065.0 89030.1 -60065.0
+ )
+ (net 3v3 1)
+ (clearance_class default)
+ )
+ )
+)
\ No newline at end of file